The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 16, 2003
Filed:
Mar. 28, 2001
Applicant:
Inventors:
Waisum Wong, El Dorado Hills, CA (US);
Chaitanya Rajguru, Folsom, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03H 1/126 ;
U.S. Cl.
CPC ...
H03H 1/126 ;
Abstract
A time delay circuit including a first transistor having a gate, a drain, a source, and a channel between the source and the drain. The input voltage is applied between the gate and drain and the output is taken between the source and drain. The output voltage follows the gate voltage, and the first transistor gate voltage is substantially constant. The time delay circuit also includes a delay element. The output voltage of the first transistor biases the delay element.