Method of fabricating flash memory device using self-aligned non-exposure pattern formation process

Abstract

A method of fabricating a flash memory device uses a self-aligned non-exposure pattern formation process. A conductive layer and an oxidation-blocking layer are formed on a stepped pattern including a floating gate pattern and an inter-gate insulating layer pattern such that the conductive layer and the oxidation-blocking layer conform to the stepped pattern. A photoresist layer is formed on the oxidation-blocking layer such that the photoresist layer has an upper surface situated above the oxidation-blocking layer. A portion of the photoresist layer is dissolved, without having photo-exposed the photoresist layer, by soaking the photoresist layer in developing solution. This soaking alone, or supplemented with an etch back process, is carried out until the upper surface of the photoresist layer is situated below the upper surface of the oxidation-blocking layer on the stepped pattern. The resulting photoresist pattern exposes that part of the oxidation-blocking layer on the stepped pattern. A blocking layer pattern exposing the conductive layer is formed on the stepped pattern by removing the exposed part of the oxidation-blocking layer. The photoresist pattern is then removed. A hard mask defining a control gate is formed by oxidizing the surface of the conductive layer exposed by the blocking layer pattern. The blocking layer pattern is then removed. A control gate is formed by etching the conductive layer using the hard mask as an etch mask. The hard mask is then removed whereupon a stacked gate structure is formed.