The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2003
Filed:
Nov. 13, 2002
Ching-Hsiang Hsu, Hsin-Chu, TW;
Yen-Tai Lin, Hsin-Chu, TW;
Chih-Hsun Chu, Hsin-Chu, TW;
Shih-Jye Shen, Hsin-Chu, TW;
Ching-Sung Yang, Chang-Hua Hsien, TW;
Ming-Chou Ho, Hsin-Chu, TW;
eMemory Technology Inc., Hsin-Chu, TW;
Abstract
An electrically erasable programmable logic device (EEPLD) includes a P type semiconductor substrate. An N type well is formed on the P type semiconductor substrate. A first PMOS transistor is formed on the N well. The first PMOS transistor comprises a floating gate, a first P doped region serving as a drain of the first PMOS transistor, and a P doped region encompassing an N doped region for erasing the first PMOS transistor. A second PMOS transistor is also formed on the N well and serially connected to the first PMOS transistor. The first P doped region functions as a source of the second PMOS transistor, and the second PMOS transistor further comprises a select gate and a second P doped region serving as a drain of the second PMOS transistor.