The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2003
Filed:
Jun. 30, 2000
Kalyan Muthukumar, Cupertino, CA (US);
David A Helder, Holland, MI (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
The present invention provides a mechanism for implementing compare speculation in software pipelined loops. A data dependency graph (DDG) is generated for a loop that includes a control compare instruction, a compare instruction and a non-speculative instruction that depends directly or indirectly on the compare instruction. A loop-carried edge between the control compare instruction and the compare instruction is replaced by a loop-carried edge between the control compare instruction and the non-speculative instruction. If the compare instruction is speculated when the loop is modulo-scheduled, any load instruction that depends on the compare is converted to a speculative load, and a loop-carried edge is added between the control compare and a check instruction associated with the speculative load. A loop-independent edge is also added between the check instruction and the non-speculative instruction if the non-speculative instruction also depends on the load.