The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 2003
Filed:
Feb. 26, 2001
Teppei Hirotsu, Hitachi, JP;
Ryo Fujita, Hitachi, JP;
Kotaro Shimamura, Hitachinaka, JP;
Hiromichi Yamada, Hitachi, JP;
Dai Fujii, Hitachi, JP;
Haruyuki Nakayama, Palo Alto, CA (US);
Hitachi, Ltd., Tokyo, JP;
Abstract
In logical compound of inter-subblock paths, circuits including all inter-subblock paths are generated. Logical compound is conducted for the generated circuits to achieve logical compound of the inter-subblock paths. By treating inter-subblock paths as intra-subblock paths, no input/output delay restriction is required for the logical compound of inter-subblock paths. This makes it possible to fully use performance of the logical compound tool, and hence the inter-subblock paths can be optimized through one operation of the processing.