The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2003

Filed:

Nov. 15, 2000
Applicant:
Inventors:

Paul H. Bergeron, South Burlington, VT (US);

Keith M. Carrig, Essex Junction, VT (US);

Alvar A. Dean, Groton, MA (US);

Roger P. Gregor, Endicott, NY (US);

David J. Hathaway, Underhill Center, VT (US);

David E. Lackey, Jericho, VT (US);

Harold E. Reindel, Williston, VT (US);

Larry Wissel, Williston, VT (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

A method and structure of clock optimization including creating an initial placement of clock feeding circuits according to clock signal requirements; identifying clusters of the clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within the cluster is connected; changing pin connections between the clock feeding circuits and clock signal supply devices to switch selected ones of the clock feeding circuits to different clusters to reduce lengths of wires between the clock feeding circuits and the clock signal supply devices within each cluster; and adjusting positions of the clock feeding circuits within design constraints to further reduce the lengths of the wires.


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