The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 2003
Filed:
Jan. 28, 1998
Robert Kraft, Plano, TX (US);
Scott H. Prengle, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A five step, low pressure, high-density-plasma etch process used to etch complicated DRAM transistor gate stacks with high inter-layer selectivity. Such stacks typically consist of the following layers: silicon nitride ( ), tungsten ( ), titanium nitride ( ), and polysilicon ( ). The process includes one step for each of the four layers in the gate stack, and one step to ash the photoresist. These five process steps can preferably be performed in four separate chambers on a cluster tool platform. The innovative etch process of the present invention fabricates gates with lengths of 0.25 microns and below with excellent profile, excellent linewidth uniformity across the wafer, and minimal loss of the gate oxide.