The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2003

Filed:

Nov. 29, 2001
Applicant:
Inventors:

Shoji Seta, Yokohama, JP;

Makoto Sekine, Yokohama, JP;

Naofumi Nakamura, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1391 ;
U.S. Cl.
CPC ...
H01L 2/1391 ;
Abstract

There is provided a method of forming an interlayer insulating film having a dual-damascene structure, a contact hole and a deep trench mask using an organic silicon film. The shape of polysilane or the like is processed so that polysilane is used as an interlayer insulating film having a dual-damascene structure to control the shape and depth and prevent borderless etching which must be solved when a trench is formed. Polysilane and an insulating film are formed into a laminated structure so as to be integrated with each other after a dry etching step has been completed to easily form a contact hole having a high aspect ratio. The surface of polysilane is selectively formed into an insulating film so as to be used as a mask for use in a dry etching step. Polysilane for use as an anti-reflective film or an etching mask is changed to an oxide film or a nitride film so that films are easily removed. Hence it follows that a device region and a device isolation region of a densely integrated circuit can be smoothed, a self-aligned contact hole and metallization trench can be formed with a satisfactory manufacturing yield and the pattern of a gate electrode can be formed.


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