The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 2003
Filed:
Feb. 13, 2001
Mark E. Jost, Boise, ID (US);
David J. Hansen, Boise, ID (US);
Steven M. McDonald, Meridian, ID (US);
Other;
Abstract
A semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, a) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein; and b) while fabricating integrated circuitry elsewhere on the wafer, processing a first portion of at least one of the alignment patterns differently from a second portion of the one alignment pattern to render the first portion to be different from the second portion in the one alignment pattern. Such preferably superimposes a secondary step, most preferably of the same degree, over only a portion of the elevation steps in at least one of the wafer alignment patterns. Further, a semiconductor processing method of forming integrated circuitry on a semiconductor wafer includes, i) forming at least two discrete wafer alignment patterns on the wafer, the two discrete alignment patterns having respective series of elevation steps provided therein; and ii) while fabricating integrated circuitry elsewhere on the wafer, processing one of the alignment patterns differently from the other to render the one alignment pattern to be different from the other alignment pattern.