The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2003
Filed:
Oct. 26, 2001
Ronald G. Filippi, Jr., Wappingers Falls, NY (US);
Alvin W. Strong, Essex Junction, VT (US);
Timothy D. Sullivan, Underhill, VT (US);
Deborah Tibel, South Burlington, VT (US);
Michael Ruprecht, Essex Junction, VT (US);
Carole Graas, Jericho, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for determining the electromigration characteristics of a wiring structure in an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes configuring a defined test structure type for the integrated circuit device. The defined test structure type further includes a first line of wiring primarily disposed in a principal plane of a semiconductor substrate, and a second line of wiring connected to the first line of wiring. The second line of wiring is disposed in a secondary plane which is substantially parallel to the principal plane, with the first and second lines of wiring being connected by a via structure therebetween. A thermal coefficient of resistance for the first line of wiring and the via structure is determined, and a wafer-level stress condition is introduced in a first individual test structure of the defined test structure type. Then, at least one parameter value for is determined for the first individual test structure, which parameter value is used to predict a lifetime projection for the wiring structure in the integrated circuit device.