The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2003
Filed:
Oct. 20, 2000
Applicant:
Inventors:
Hiroyuki Uchiyama, Tachikawa, JP;
Hiraku Chakihara, Akishima, JP;
Teruhisa Ichise, Ome, JP;
Michimoto Kaminaga, Hitachinaka, JP;
Assignee:
Other;
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/7108 ; H01L 2/976 ; H01L 3/1119 ; H01L 2/348 ;
U.S. Cl.
CPC ...
H01L 2/7108 ; H01L 2/976 ; H01L 3/1119 ; H01L 2/348 ;
Abstract
A large area dummy pattern DL is formed in a layer underneath a target T region formed in a scribe region SR of a wafer. A small area dummy pattern in a lower layer and a small area dummy pattern Ds in an upper layer are disposed in a region where the inter-pattern space of a pattern (active regions L , L , L , gate electrode ), which functions as an element of a product region PR and scribe region SR, is wide. The small area dummy pattern Ds in the upper layer is offset by ½ pitch relative to the small area dummy pattern Ds in the lower layer.