The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2003
Filed:
Aug. 18, 2000
Robert J. Madge, Portland, OR (US);
Emery Sugasawara, Pleasanton, CA (US);
W. Robert Daasch, West Linn, OR (US);
James N. McNames, Portland, OR (US);
Daniel R. Bockelman, Portland, OR (US);
Kevin Cota, Portland, OR (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method for testing integrated circuits having associated position designations, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by the position designations. The output from at least a subset of the integrated circuits is selected and mathematically manipulated to produce a reference value. The output for each of the integrated circuits in the selected subset is individually compared to the reference value, and graded integrated circuits within the selected subset that have output that differs from the reference value by more than a given amount are identified. A classification is assigned to the graded integrated circuits and recorded in the wafer map, referenced by the position designations for the graded integrated circuits.