The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2003
Filed:
Nov. 23, 1999
Debendra Das Sharma, Santa Clara, CA (US);
Ashish Gupta, Cupertino, CA (US);
Donald A. Williamson, Cupertino, CA (US);
Hewlett-Packard Development Companay, L.P., Houston, TX (US);
Abstract
A function for verifying an asynchronous boundary behavior of a digital system. The asynchronous boundary is formed at a coupling between a first series of registers clocked by a write clock (the write domain), and a second series of registers clocked by a read clock (the read domain). A delay register and multiplexer are inserted after a predetermined register within the digital system, where the predetermined register and delay register are clocked by the same clock. The output of the predetermined register is coupled to both the first input of multiplexer and a first input of the delay register. The delay register is coupled to the second input of the multiplexer. A selector is coupled to the multiplexer for selecting which of the two multiplexer inputs to pass to subsequent registers in the digital system. By inserting the delay register/multiplexer at or after the asynchronous boundary, any signal level uncertainty present between the read domain and the write domain is captured and propagated through the digital system.