The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2003

Filed:

Jan. 21, 2000
Applicant:
Inventors:

Chik Patrick Yue, Milpitas, CA (US);

Siu-Weng Simon Wong, Palo Alto, CA (US);

David Kuochieh Su, Mountain View, CA (US);

William John McFarland, Los Altos, CA (US);

Assignee:

Atheros Communications, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02H 3/20 ;
U.S. Cl.
CPC ...
H02H 3/20 ;
Abstract

An ESD protection circuit uses an inductor to create an electromagnetic resonance in conjunction with the load capacitance of a conventional ESD device. By properly tuning the resonance of this combination, the protective properties of the ESD device can be maintained while minimizing its capacitive load on the main circuit. The inductor can be interposed in various series configurations with the ESD device between the main circuit and a voltage rail; alternatively, the inductor can be connected in various configurations in parallel with the ESD device. The inductor may be implemented as an on-chip inductor using conventional IC fabrication technologies, or may be implemented using IC chip bonding wires as inductors.


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