The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2003
Filed:
Nov. 14, 2000
Applicant:
Inventor:
Hirotomo Miura, Tokyo, JP;
Assignee:
United Microelectronics Corporation, Taiwan, CH;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1335 ; H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1335 ; H01L 2/1336 ;
Abstract
A semiconductor device has a semiconductor substrate and a conductive layer formed above the semiconductor substrate. The conductive layer has a silicon film, a silicide film formed on the silicon film, and a high melting-point metal film formed on the silicide film. The silicon film has a non-doped layer, which does not contain impurities, and an impurity layer which is formed on the non-doped layer and contains impurities. The silicide film is formed on the impurity layer of the silicon film.
Quick Actions:
Miura, Hirotomo. (2003). Method for fabricating a semiconductor device having a impurity layer disposed between a non-doped silicon film and high melting-point metal film for reducing solid state reaction between said high melting-point metal film and polycrystal silicon film (U.S. Patent No. 6596567). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6596567
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile