The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2003

Filed:

Nov. 22, 2000
Applicant:
Inventors:

Mark W. Randolph, San Jose, CA (US);

Shane Charles Hollmer, San Jose, CA (US);

Pau-Ling Chen, Saratoga, CA (US);

Richard M. Fastow, Cupertino, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/973 ;
U.S. Cl.
CPC ...
H01L 2/973 ;
Abstract

An array of memory cells includes a plurality of memory cells interconnected via a grid of M wordlines and M bitlines, wherein M=2, 3, 4, 5, . . . wherein each of the M bitlines is buried. The array further includes a plurality of contacts, wherein each of the plurality of contacts is formed every N wordlines, N=1, 2, 3, . . . , wherein each of the plurality of contacts overlies a gate of a different one of the plurality of memory cells. A strap connects one of the buried bitlines to a gate that underlies one of the plurality of contacts, and wherein contacts overlying a first bit line are staggered with respect to contacts overlying a second bit line that is adjacent to the first bit line.


Find Patent Forward Citations

Quick Actions:

Randolph, Mark. (2003). Staggered bitline strapping of a non-volatile memory cell (U.S. Patent No. 6593606). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6593606

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