The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2003
Filed:
Jul. 17, 2001
Edward O. Travis, Austin, TX (US);
Aykut Dengi, Tempe, AZ (US);
Sejal Chheda, Austin, TX (US);
Tat-Kwan Yu, Cupertino, CA (US);
Mark S. Roberton, Los Angeles, CA (US);
Ruiqi Tian, Pflugerville, TX (US);
Robert E. Boone, Austin, TX (US);
Alfred J. Reich, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).