High speed sink/source register to reduce level sensitive scan design test time

Abstract

Test data is provided through shift registers, operated at a high clock rate comparable to or exceeding a normal high speed clock rate of a chip being tested, to each of a plurality of scan chains configured from registers present on the chip; respective latches of which are connected to inputs and outputs of logic array partitions to be tested. Reduced test clock rate of input and output circuits of the scan chains is accommodated by high speed source and sink shift registers. The source and sink registers are fully loaded and unloaded between consecutive test clock signals and test signals are preferably applied to and collected from the chip in a single serial string through a single pair of tester input/output pins. Testing time is thus reduced without requiring design time and chip space for a clock tree optimized for high speed operation while use of testers of reduced cost and having an arbitrarily small number of input/output pin pairs and independent of test register configuaration on the chip can be used.