The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2003
Filed:
Apr. 23, 2001
Applicant:
Inventors:
Jeongjin Roh, Austin, TX (US);
Vijayakumaran V. Nair, Austin, TX (US);
Jiang Chen, Austin, TX (US);
Rose W. Wang, Chandler, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 3/00 ;
U.S. Cl.
CPC ...
H03M 3/00 ;
Abstract
An analog to digital converter may achieve an output sampling rate that is not an integer multiple of the system clock. This may be done without using the conventional phase-locked loop circuit that generally requires a longer design time, more testing, and more silicon area. A pseudo clock may be generated from the system clock in which some of the system clock pulses are disabled to achieve a pseudo clock with the desired effective frequency.