The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6590237 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 08, 2003

Filed:

Jun. 12, 2001
Applicant:
Inventor:

Jei-Hwan Yoo, Kyunggi-do, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/710 ;
U.S. Cl.
CPC ...
H01L 2/710 ;
Abstract

A layout structure of a semiconductor memory device having a memory cell array region, a word line drive region proximate the memory cell array, a bit line equalization region spaced apart from the memory cell array region, an impurity region formed between the memory cell array region and the bit line equalization region electrically coupled to the bit line equalization region, and a metal line supplying a bit line equalization voltage to the impurity region, wherein a contact connecting the metal line and the impurity region is formed lateral to the word line drive region rather than between the memory cell array region and the bit line equalization region, so that no contacts are formed directly between the memory cell array region and the bit line equalization region.


Find Patent Forward Citations

Yoo, Jei-Hwan. (2003). Layout structure for dynamic random access memory (U.S. Patent No. 6590237). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6590237

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…