The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2003
Filed:
Jun. 12, 2000
Richard D. Reohr, Jr., Hillsboro, OR (US);
Brian M. Collins, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A device and method to test a circuit in a chip that has memory embedded in the chip using a scan chain. This device and method generates a known signal simultaneously to a bypass circuit and the memory onboard the chip. The bypass circuit uses a series of exclusive OR gates, a flip-flop, and a multiplexer to receive the known signal. The exclusive OR gates reduce the number of signals input so that they match the number of signals output by memory. A flip-flop is used to store the data received from the exclusive OR gates and transfer it to a multiplexer. The multiplexer receives data from memory and the flip-flop and selects which data to pass on in the circuit. When a scan test is being run on the circuit the multiplexer passes on only the data from the flip-flop. When a scan test is not being run the multiplexer only passes on the data from memory. This device and method allows for circuits to be tested using a scan chain that could not otherwise be tested due to the presence of memory embedded in the chip.