The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2003

Filed:

Aug. 16, 2002
Applicant:
Inventor:

Werner Graf, Dresden, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

Integrated semiconductor circuits have MOS transistors whose gate electrodes are provided with dopings in order to set the electrical potential of the channel area by changing the ionization energy (work function) of the electrons. Transistors in semiconductor circuits, which have both a memory area and a logic area, are produced either using different dopings for pMOS and NMOS transistors in the logic area (dual work function) or using common source/drain electrodes in the memory area (borderless contact), with all the transistors in the semiconductor circuit receiving the same gate doping in the latter case. A method is proposed by which a dual work function and a borderless contact can be produced at the same time. Furthermore, the method results without any additional effort in a trench between the gate layer stacks of the memory area and of the logic area, which prevents lateral ion diffusion.


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