The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 2003
Filed:
Aug. 09, 2001
Matthew Ryskoski, Kyle, TX (US);
Advanced Micro Devices, Inc., Austin, TX (US);
Abstract
In one illustrative embodiment, the method comprises performing at least one electrical performance test on an integrated circuit device, determining, based upon data obtained from said at least one electrical performance test, a target thickness for at least one inter-level dielectric layer to be formed above a wafer, and performing a deposition process to form said at least one inter-level dielectric layer to said target thickness. In other embodiments, the method comprises determining a duration of a deposition process to be performed to form the at least one inter-level dielectric layer, and performing the deposition process for the determined duration. In another aspect, the present invention is directed to a system that comprises an electrical metrology tool adapted to perform at least one electrical test on an integrated circuit device, a controller that determines, based upon data obtained from said at least one electrical performance test, a target thickness for at least one inter-level dielectric layer to be formed above a wafer, and a deposition tool for performing a deposition process to form the inter-level dielectric layer to the target thickness.