The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2003
Filed:
May. 12, 2000
Chuan-Yu Wang, Sunnyvale, CA (US);
Ping-Hann Peter Wang, Mountain View, CA (US);
Yi-Min Jiang, San Jose, CA (US);
Synopsys, Inc., Mountain View, CA (US);
Abstract
A genetic algorithm (GA) based approach to optimize integrated circuit designs for power dissipation. The genetic algorithm optimization process efficiently generates tight lower bounds of the peak power dissipation for a given integrated circuit design. In this approach, the power within a given integrated circuit design circuit is viewed as a function in terms of a set of stimuli to primary inputs of the integrated circuit design. Maximization of the function, and hence, the power dissipation is guided by the genetic algorithm. By repeatedly stimulating the integrated circuit design and measuring the corresponding response, the genetic algorithm process efficiently explores the solution space to obtain a maximization of the function. The genetic algorithm process is implemented within a computer-based EDA (electronic design automation) synthesis system. The EDA synthesis system executes the computer implemented steps of accessing a circuit netlist representing an integrated circuit design to be realized in physical form, defining a function that describes the power with respect to stimulation, maximizing the function by using a genetic algorithm to obtain a set of stimulation inputs which generate a maximum power dissipation, and optimizing power dissipation for the circuit netlist by optimizing those portions of the circuit netlist identified by the set of stimulation inputs.