The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 10, 2003

Filed:

May. 01, 2002
Applicant:
Inventors:

Rajesh Kumar, Kariya, JP;

Takamasa Suzuki, Nagoya, JP;

Assignee:

Denso Corporation, Kariya, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01K 2/978 ; H01K 3/1028 ;
U.S. Cl.
CPC ...
H01K 2/978 ; H01K 3/1028 ;
Abstract

A channel layer is formed on an n -type epitaxial layer and first gate areas and field enhanced area(s) and second gate areas are formed on the first gate areas Furthermore, n -type source areas and a third gate area are formed on the second gate areas These steps result in a device structure having a first J-FET with the n -type source areas and the n -type substrate as a source and drain and the first gate areas at the right and left in the figure as a gate; and the second J-FET with the n -type source areas and the n -type substrate as a source and drain and the second gate areas and the third gate area as a gate. The first J-FET is normally-on, while the second J-FET is normally-off.


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