The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2003
Filed:
Nov. 14, 2000
Kenneth A. Bandy, Milton, VT (US);
Stuart D. Cheney, Essex Junction, VT (US);
Gary L. Milo, Williston, VT (US);
Yutong Wu, South Burlington, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention is intended for use on BiCMOS technology where the BJTs are formed after the FETs. A thin FET protection layer is deposited on the raised and recessed regions of the semiconductor substrate A selectively removable filler layer is then deposited on the FET protection layer with a thickness to over-fill the recessed regions of the gates of the FETs. The selectively removable filler layer is then planarized until the FET protection layer on top of the gates is exposed. The recessed regions between the gates are left substantially filled with selectively removable filler layer The selectively removable filler layer in the region where the BJT is formed is patterned and an opening is made to allow for the depositing of layers of different materials used in the construction of the BJT. The layer of different materials are processed by methods known in the art to form polysilicon emitter of the BJT. Due to selectively removable filler layer creating a substantially planar surface in the recessed regions of the FETs, little to none of the layers of different materials that are used in the construction of the BJT are deposited within the recessed regions Thus, removal of the layers of different materials ( ′), from the FET region is simplified. After removal of the layers of different materials ( ′), from the FET region, the selectively removable filler layer is removed selectively to the FET protection layer The FET protection layer is then removed. The recessed regions between the gates of the FETs are free from residual films.