The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2003
Filed:
Aug. 16, 1999
Applicant:
Inventor:
Glen R. Anderson, Palo Alto, CA (US);
Assignee:
Sequence Design, Inc., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
An embodiment of the present invention is a method for logic synthesis that reduces use of computer memory and reduces computer runtime. In particular, an embodiment of the present invention is a method for logic synthesis which includes the steps of: (a) analyzing an HDL model to develop a parse tree and (b) elaborating the parse tree to create a word-oriented netlist.
Anderson, Glen. (2003). Method and apparatus for logic synthesis (word oriented netlist) (U.S. Patent No. 6574787). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6574787
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile