On-line testing of the programmable interconnect network in field programmable gate arrays

Abstract

A method of self-testing the programmable routing network in a field programmable gate array (FPGA) during normal on-line operation includes configuring the FPGA into an initial self-testing area and a working area. The initial self-testing area is preferably configured to include an horizontal self-testing area primarily for testing horizontal wire segments and a vertical self-testing area primarily for testing vertical wire segments. Programmable logic blocks located within the self-testing areas are configured to function as a test pattern generator and an output response analyzer, and a portion of the programmable routing resources within the self-testing areas is configured as groups of wires under test. An exhaustive set of test patterns generated by the test pattern generator is applied to the groups of wires under test which are repeatedly reconfigured in order to completely test the programmable routing resources within the self-testing areas. The outputs of the groups of wires under test are compared by the output response analyzer and resultant fault status data for each group of wires under test is received by a controller in communication with a memory for storing the fault status data. After completely testing the programmable routing resources in one of the initial self-testing areas, the FPGA is reconfigured such that a portion of the working area becomes a subsequent self-testing area and at least a portion of one of the initial self-testing areas replaces that portion of the working area. In other words, the self-testing areas rove around the FPGA repeating the steps of testing and reconfiguring until the entire FPGA has undergone testing or continuously.