The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2003
Filed:
Jul. 11, 2002
Applicant:
Inventors:
Satchit Jain, San Jose, CA (US);
Sun-Soo Cho, Sunnyvale, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 ; G06F 1/08 ; G06F 1/10 ; G06T 1/60 ; G05F 1/10 ;
U.S. Cl.
CPC ...
G06F 1/32 ; G06F 1/08 ; G06F 1/10 ; G06T 1/60 ; G05F 1/10 ;
Abstract
An integrated circuit contains a central processing unit (“CPU”), a graphic control hub (“GCH”), a memory control hub (“MCH”), and a phase lock loop (“PLL”). The GCH, MCH, and PLL are coupled to the CPU. The MCH controls memory transactions. The PLL is configured to allow the CPU to operate at more than one power consumption states.
Jain, Satchit. (2003). Method and apparatus to control processor power and performance for single phase lock loop (pll) processor systems (U.S. Patent No. 6574738). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6574738
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile