Trench transistor structure and formation method

Abstract

A trench transistor formation method for creating source and drain regions and source and drain extension regions having an idealized doping profile using a single dopant implantation step. In one embodiment, the present invention is comprised of a method which includes forming a trench having sidewalls and a bottom into a substrate. The present embodiment also recites forming sidewalls spacer regions along at least a portion of the sidewalls of the trench. Subsequently, the present embodiment forms a gate dielectric along at least a portion of the bottom of the trench, and deposits a gate metal within the trench. The present embodiment then subjects the substrate to an etching process such that the top surface of the substrate is lower than the top surface of the sidewall spacer regions formed along the sidewalls of the trench. The present embodiment then performs a single dopant implantation step which results in the formation of both the source and drain regions and the source and drain extension regions wherein the source and drain regions have an implantation depth which is greater than the implantation depth of the source and drain extension regions. Additionally, substantially no dopant is implanted within a channel region residing beneath the gate metal disposed within the trench. In so doing, an idealized dopant profile is achieved within the trench transistor using the single dopant implantation step.