The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2003

Filed:

May. 24, 2001
Applicant:
Inventors:

Shamouil Shamoulian, San Jose, CA (US);

Arnold Kholodenko, San Francisco, CA (US);

Senh Thach, Union City, CA (US);

Wing Cheng, Sunnyvale, CA (US);

Assignee:

Applied Materials Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B22F 7/04 ;
U.S. Cl.
CPC ...
B22F 7/04 ;
Abstract

A method of fabricating a semiconductor wafer support chuck apparatus having a first sintered layer and a second sintered layer. The method comprising the steps of providing the first sintered layer having a plurality of gas distribution ports and providing the second sintered layer having a plurality of grooves. The first sintered layer is stacked on top of the second sintered layer, where a diffusion bonding layer is disposed between the first sintered layer and the second sintered layer. Thereafter, the stacked first and second sintered layers are resintered such that the diffusion bonding layer joins the first and second sintered layers together to form a semiconductor wafer support apparatus.


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