Initial stage of a multi-stage algorithmic pattern generator for testing ic chips

Abstract

An initial stage of a multi-stage algorithmic pattern generator which generates bit streams for testing IC chips, is comprised of multiple sets of input registers which store respective addresses; and an address modifying circuit that is coupled to the input registers, which receives commands, and in response, selects one register in one set and generates a modified address by performing arithmetic operations on the address in the selected register. Also, the initial stage includes a boundary check circuit that is coupled to the address modifying circuit, which stores a respective minimum limit and a respective maximum limit for each register set. This initial stage is particularly useful in generating sequences of addresses for memory cells in a chip that is to be tested, where the cells are arranged in rows and columns. When a particular Min/Max limit for a row/column is reached, then that event is remembered by the boundary check circuit. Thereafter, when the next row/column address is generated, the boundary check circuit automatically replaces the generated address (which will exceed the limit) with the proper address. This operation of detecting a limit address in one cycle, and replacing the next generated address in a subsequent cycle, enables the cycle time of the initial stage to be shorter than it otherwise could be if detection outside the limit and replacement with the proper address, occur in a single cycle.