The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2003
Filed:
Jul. 25, 2001
Shen Lin, Foster City, CA (US);
Norman Chang, Fremont, CA (US);
Keunmyung Lee, Palo Alto, CA (US);
Osamu Nakagawa, Redwood City, CA (US);
Weize Xie, Cupertino, CA (US);
Hewlett-Packard Development Company L.P., Houston, TX (US);
Abstract
A system and method is provided for controlling clock skew to meet timing constraints for a semiconductor integrated circuit. On-chip self-tuning circuits can be connected to each latch in the integrated circuit for controlling clock skew. Each self-tuning circuit delays a clock signal that is input to a latch when the clock skew does not satisfy the timing constraint for that latch. The self-tuning circuit repeatedly delays the clock signal until the clock skew is satisfied or until the delay becomes greater than or equal to a predetermined threshold. The delayed clock signal is then pushed to other latches in the integrated circuit until all the timing constraints for the integrated circuit are satisfied.