The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2003

Filed:

Dec. 29, 1997
Applicant:
Inventor:

Ray Askew, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 9/00 ;
U.S. Cl.
CPC ...
H05K 9/00 ;
Abstract

Improved electromagnetic compatibility for integrated motherboard or device board designs is provided by magnetic shielding, electric shielding, or both integrated into the chip packaging materials. Motherboard emissions may be reduced by use of the shielding. A nonconductive primary and tertiary layer sandwich a high-conductivity metal secondary layer forming a Faraday cage for electric field shielding. A nonconductive primary layer is covered by a tertiary layer formed of a composite having permeable material for magnetic shielding. The tertiary layer formed of a composite could include a high permeability particulate ferrous material. Both the secondary layer and the tertiary layer formed of a composite could be used for both electric and magnetic shielding of chips.


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Askew, Ray. (2003). Magnetic and electric shielding of on-board devices (U.S. Patent No. 6566596). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6566596

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