The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2003
Filed:
Oct. 02, 2000
Andrej A. Zolotykh, Moskovskaya Oblast, RU;
Elyar E. Gasanov, Moscow, RU;
Alexander S. Podkolzin, Moscow, RU;
Valery B. Kudryavtsev, Moscow, RU;
LSI Logic Corporation, Milpitas, CA (US);
Abstract
The present invention comprises method for optimizing an integrated circuit design that includes computing of capacities and delays of an integrated circuit design, resynthesizing said integrated circuit design utilizing a plurality of local optimization procedures, and removing overlap the local optimization procedures can include a local resynthesis of logic trees procedure that utilizes multiple cost functions, a dynamic buffer and inverter tree optimization procedure, and a cell resizing procedure. Generally, faster local optimization procedures are applied first and slower, more thorough procedures are applied to areas where the faster procedures have not solved the optimization tasks.