Nor-structured semiconductor memory device

Abstract

A NOR-structured semiconductor memory device with a novel configuration of bit line connection is disclosed. The NOR-structured semiconductor memory device comprises a semiconductor memory cell array electrically connected to a plurality of bit lines. The plurality of bit lines are divided into at least four bit line groups. At least two bit lines of each bit line group are coupled to a main bit line through at least two bit line transistors, respectively. Furthermore, the bit lines of the NOR-structured semiconductor memory device are arranged in such a way that at least four adjacent bit lines thereof are selected from four different bit line groups and coupled to four different main bit lines, respectively. During a programming or data reading operation, two adjacent bit lines of the four adjacent bit lines are supplied with a programming voltage or sense current while the other two adjacent bit lines are grounded. Therefore, the NOR-structured semiconductor memory device successfully prevents the programming disturbance or correctly determines the data stored in memory cells at a high speed because no leakage current path is formed.