The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2003

Filed:

Nov. 25, 1998
Applicant:
Inventors:

Kiyohiko Sakakibara, Tokyo, JP;

Hirotada Kuriyama, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
A01L 2/9788 ;
U.S. Cl.
CPC ...
A01L 2/9788 ;
Abstract

A non-volatile semiconductor memory device comprising: a semiconductor substrate, memory cells, a region of memory cell array in which said memory cells are arranged in a matrix-like form, a region of peripheral circuit, a connecting region for connecting said region of memory cell array to said region of peripheral circuit, and conductive layers provided closest to said substrate with intervals between each other, wherein said intervals of said conductive layers are substantially equal to each other in said region of memory cell array and said connecting region, whereby when insulating films are formed and planarized after forming said conductive layers, it is possible to restrict producing of seams in the insulating films at stripped portions of the conductive layers.


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