The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 13, 2003
Filed:
Nov. 06, 2001
Consolidation method of junction contact etch for below 150 nanometer deep trench-based dram devices
Brian Lee, Hsinchu, TW;
ProMos Technologies, Inc., Hsin-chu, TW;
Abstract
A consolidated junction contact etch in the fabrication of a DRAM integrated circuit device is described. Semiconductor device structures are provided in and on a substrate wherein the substrate is divided into an active area and a periphery area. The semiconductor device structures are covered with an etch stop layer. A dielectric layer is deposited over the etch stop layer. The dielectric layer is concurrently etched through in the active area to form bit line contact openings, in the periphery area to form substrate contact openings, and to form gate contact openings wherein the etching stops at the etch stop layer. The etch stop layer is etched into to a lesser extent through the substrate contact openings and the bit line contact openings than through the gate contact openings. Then, the etch stop layer is etched through using a directional etch selective to the etch stop layer. The bit line contact openings, substrate contact openings, and gate contact openings are filled with a conducting layer to complete formation of contacts in the fabrication of a DRAM integrated circuit device.