Wafer level burn-in and electrical test system and method

Abstract

A burn-in and electrical test system ( ) includes a temperature controlled zone ( ) and a cool zone ( ) separated by a transition zone The temperature controlled zone ( ) is configured to receive a plurality of wafer cartridges ( ) and connect the cartridges ( ) to test electronics ( ) and power electronics ( ), which are mounted in the cool zone ( ). Each of the wafer cartridges ( ) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics ( ) consists of a pattern generator PCB ( ) and a signal driver and fault analysis PCB ( ) connected together by a parallel bus ( ). The pattern generator PCB ( ) and the fault analysis PCB ( ) are connected to a rigid signal probe PCB ( ) in cartridge ( ) to provide a straight through signal path. The probe PCB ( ) is rigid in order to allow close control of capacitance between each signal line and a backplane, thus providing impedance controlled interconnections between a semiconductor wafer under test and the test electronics ( ). The power distribution system ( ) is connected to a probe power PCB ( ) in the cartridge ( ). The probe power PCB ( ) has at least a bendable portion in order to allow it to be positioned closely adjacent to and parallel with the rigid probe PCB ( ), yet extend a substantial distance away from the probe PCB ( ) at its interconnection ( ).