The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 06, 2003
Filed:
Oct. 11, 2000
Carlos A. Paz de Araujo, Colorado Springs, CO (US);
Larry D. McMillan, Colorado Springs, CO (US);
Vikram Joshi, Colorado Springs, CO (US);
Narayan Solayappan, Colorado Springs, CO (US);
Joseph D. Cuchiaro, Colorado Springs, CO (US);
Symetrix Corporation, Colorado Springs, CO (US);
Abstract
An integrated circuit includes a layered superlattice material having the formula A A . . . Aj S S . . . Sk B B . . . Bl Q , where A , A . . . Aj represent A-site elements in a perovskite-like structure, S , S . . . Sk represent superlattice generator elements, B , B . . . B represent B-site elements in a perovskite-like structure, Q represents an anion, the superscripts indicate the valences of the respective elements, the subscripts indicate the number of atoms of the element in the unit cell, and at least w and y are non-zero. Some of these materials are extremely low fatigue ferroelectrics and are applied in ferroelectric FETs in non-volatile memories. Others are high dielectric constant materials that do not degrade or break down over long periods of use and are applied as the gate insulator in volatile memories.