The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 29, 2003
Filed:
Oct. 12, 2001
Aritharan Thurairajaratnam, Freemont, CA (US);
Pradip D. Patel, Redwood City, CA (US);
Manickam Thavarajah, San Jose, CA (US);
Hong T. Lim, San Jose, CA (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method of forming a via in a circuit, such that parasitic capacitance is reduced. The surface layers of the circuit are identified, to which continuity with the via is desired, and secondary layers of the circuit are also identified. Via lands are formed only on the surface layers and not on the secondary layers. The via lands are formed in first portions of the surface layers, where the via is to pass through the surface layers. Nonconductive cut outs are formed in second portions of the secondary layers where the via is to pass through the secondary layers. The surface layers and the secondary layers of the circuit are laminated together. The first portions of the surface layers are aligned with the second portions of the secondary layers. A through hole is formed through the via lands formed in the surface layers, and also through the cut outs formed in the secondary layers. The via is formed in the through hole. The parasitic capacitance of the via is reduced by not having via lands on the secondary layers.