The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2003

Filed:

Jun. 19, 2002
Applicant:
Inventor:

Takahisa Yamaha, Hamamatsu, JP;

Assignee:

Yamaha Corp., , JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/128 ;
U.S. Cl.
CPC ...
H01L 2/128 ;
Abstract

A first wiring layer is formed on an insulating film. The first wiring layer is formed by sequentially laminating a barrier layer, an Al alloy layer, and an antireflection layer. The antireflection layer is formed by sequentially laminating a Ti layer, a TiN layer, and a TiON layer. After an interlayer insulating film is formed on the first wiring layer, a contact hole is formed through the interlayer insulating film and a tight adhesion layer is formed on an inner surface of the contact hole. The tight adhesion layer is formed by sequentially laminating a Ti layer, a TiN layer, a TiON layer, and a TiN layer. A W plug is embedded in the contact hole through CVD using WF . Thereafter, an Al alloy layer and an antireflection layer are sequentially deposited and patterned to form a second wiring layer. Pin holes are not formed in the uppermost TiON layer of the first wiring layer while the contact hole is formed through etching, and diffusion of WF is intercepted by the TiON layer of the tight adhesion layer while W is deposited so that a high resistance AlF layer is not formed in the second wiring layer. Resistance of an interlayer contact area of a multi-layer wiring structure can be prevented from being increased.


Find Patent Forward Citations

Yamaha, Takahisa. (2003). Multi-layer wiring structure of integrated circuit and manufacture of multi-layer wiring (U.S. Patent No. 6555465). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6555465

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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