The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 22, 2003
Filed:
Oct. 03, 2001
Suresh Venkatesan, Austin, TX (US);
Bradley P. Smith, Gieres, FR;
Mohammed Rabiul Islam, Austin, TX (US);
Motorola, Inc., Schaumburg, IL (US);
Abstract
A dual inlaid copper interconnect structure uses a plasma enhanced nitride (PEN) bottom capping layer and a silicon rich silicon oxynitride intermediate etch stop layer. The interfaces ( and ) between these layers ( and ) and their adjacent dielectric layers ( and ) are positioned in the stack ( ) independent of the desired aspect ratio of trench openings of the copper interconnect in order to improve optical properties of the dielectric stack ( ). Etch processing is then used to position the layers ( ) and ( ) at locations within the inlaid structure depth that result in one or more of reduced DC leakage current, improved optical performance, higher frequency of operation, reduced cross talk, increased flexibility of design, or like improvements.