The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 15, 2003
Filed:
Feb. 13, 2002
In-Seak Hwang, Kyunggi-do, KR;
Si-Youn Kim, Seoul, KR;
Yoo-Sang Hwang, Kyunggi-do, KR;
Hoon Jung, Kyunggi-do, KR;
Samsung Electronics Co., Ltd., Suwon, KR;
Abstract
Cylindrical capacitors and methods of fabricating the same are provided. The cylindrical capacitor includes a cylindrical storage node stacked on a semiconductor substrate. The cylindrical storage node has a base and a stepped sidewall located on the base. The stepped sidewall has at least two sub-sidewalls, which are sequentially stacked, and at least one joint portion that connects a lower sidewall of the sub-sidewalls to an upper sidewall stacked on the lower sidewall. An upper diameter of the respective sub-sidewalls is greater than a lower diameter thereof. Also, the upper diameter of the lower sidewall is greater than the lower diameter of the upper sidewall stacked on the lower sidewall. The method of fabricating the cylindrical storage node having a stepped sidewall includes sequentially forming a plurality of molding layers over a semiconductor substrate. An etch rate of a lower molding layer of the plurality of molding layers being faster than that of an upper molding layer on the lower molding layer with respect to a predetermined etchant. The plurality of molding layers are patterned to form a preliminary storage node hole that exposes a portion of the semiconductor substrate. The patterned molding layers are isotropically etched using the etchant, thereby forming a storage node hole. Therefore, the storage node hole has a stepped sidewall profile. A conformal conductive layer is then formed on the substrate and the conductive layer is planarized until a top surface of the molding layers is exposed.