Process for forming dram cell

Abstract

A transfer FET of a DRAM cell is formed having protective dielectric layers on the top and sides of the gate electrode. A first dielectric layer, preferably silicon dioxide, is provided over the transfer FET and a self-aligned etching process is used to etch through the first dielectric layer and to open a contact via to expose one of the source/drain regions of the transfer FET. A thick layer of polysilicon is deposited over the access circuitry and in contact with the exposed source/drain region of the transfer FET. A second dielectric layer is deposited over the surface of the thick layer of polysilicon and patterned to define a sacrificial structure on the polysilicon layer and over the one source/drain region. A third dielectric layer is deposited over the sacrificial structure and is anisotropically etched back to form sidewall spacer structures on the surface of the polysilicon layer. The sacrificial structure is removed and the spacer structures are used as a mask for shaping the thick polysilicon layer into at least part of a bottom capacitor electrode. The spacers are removed and a layer of hemispherical grained polysilicon (HSG-Si) is deposited over the surface of the etched thick polysilicon layer and etched back to transfer the textured surface of the HSG-Si to the underlying conventional polysilicon. A bottom capacitor electrode mask is used to define the lateral extent of the bottom capacitor electrode. The first dielectric layer acts as an etch stop in this process. A capacitor dielectric and a top capacitor electrode are provided to complete the DRAM cell capacitor and further processing continues to complete the DRAM.