The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2003

Filed:

Apr. 19, 2000
Applicant:
Inventors:

Ranier Florian Schnabel, Höhenkirchen, DE;

Ulrike Gruening, Munich, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

A dynamic random access memory (DRAM) formed in a silicon chip that includes a support area in which support circuitry of the memory includes a single electrical contact through two dielectric layers to a conductive layer of a gate stack of a field effect support transistor that has a capping layer through which the electrical contact passes to the gate. The DRAM also includes a memory area containing an array of memory cells each include a field effect transistor. Drain regions of the transistors of the memory cells and drain and source regions of field effect transistors of the support transistors have first electrical contacts thereto through the first dielectric layer and have second electrical contacts which pass through the second dielectric layer and electrical contact to the first electrical contacts. Forming of the second electrical contacts concurrently with the single electrical contact to the gate of the support transistor saves a processing step over prior art processes.


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