The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2003

Filed:

Jan. 18, 2000
Applicant:
Inventors:

Thomas R. Omstead, Austin, TX (US);

Panya Wongsenakhum, Austin, TX (US);

William J. Messner, Mt. Morris, NY (US);

Edward J. Nagy, Cypress Mill, TX (US);

William E Starks, Victor, NY (US);

Mehrdad M. Moslehi, Los Altos, CA (US);

Assignee:

CVC Products, Inc., Rochester, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C23C 1/600 ;
U.S. Cl.
CPC ...
C23C 1/600 ;
Abstract

A method and system for fabricating a device on a substrate with a process gas, such as with chemical vapor deposition. A reaction chamber and support chuck cooperate to form a low conductance configuration for axisymetric process gas flow over the substrate and to form a high conductance configuration for enhanced evacuation of residual process gas from the reaction chamber upon completion of the process. A dual conductance chuck has an indented region that aligns with the exhaust port of the reaction chamber to restrict process gas flow in the low conductance configuration, and that moves distal a showerhead and the exhaust port to provide reduced restriction of process gas flow for reaction chamber evacuation. The chuck includes thermal control for enhancing film deposition on the substrate and for reducing residual film deposition on the chuck. An evacuation opening in the housing provides independent evacuation of residual gas from the housing. The present invention enhance throughput of device formation by reducing purge and process cycle times.


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