Method and apparatus for local resynthesis of logic trees with multiple cost functions

Abstract

Provided are systems and techniques for optimizing an integrated circuit design, in which a critical zone is identified in an integrated circuit design and a plurality of alternative identities are applied in the critical zone in order to obtain a corresponding plurality of outcomes. Alternative representations are then identified as those of the plurality of outcomes pursuant to which at least one of ramptime and timing are improved, and a best one of the alternative representations is selected to replace into the critical zone based on specified priorities which include: (i) selecting based on reduction in ramptime violation; (ii) selecting from among alternative representations that preserve cell area based on timing improvement; and (iii) if all alternative representations increase cell area, selecting based on an evaluation of a relationship between timing decrement and area increment.