The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2003

Filed:

Sep. 19, 1997
Applicant:
Inventors:

K. Paul Muller, Wappingers Falls, NY (US);

Bertrand Flietner, Hopewell Junction, NY (US);

Klaus Roithner, Dresden, DE;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/13065 ;
U.S. Cl.
CPC ...
H01L 2/13065 ;
Abstract

A gas distribution plate ( ) for a semiconductor processing chamber ( ) includes a gas distribution plate for distributing gases across a surface of a semiconductor wafer ( ) to be processed in the chamber. The gas distribution plates has a substantially planar member having gas outlets for distributing a reactant gas across the surface of the semiconductor wafer, the gas outlet means includes a plurality of apertures ( ) defined in said planar member, the plurality of apertures having different areas at predetermined locations to adjust etching gas flow. A pump ( ) is provided for evacuating a reactant-product gas created across the surface of the semiconductor wafer during wafer processing. The pump ( ) includes a plurality of tubes extending through the planar member, the plurality of tubes having apertures, and the apertures have different areas at predetermined locations to adjust reactant gas and reactant-product gas flow wherein the gas outlets and the pump coact to substantially maintain a predetermined concentration of the reactant gas and a predetermined concentration of the reactant-product gas across the surface of the semiconductor wafer during wafer processing.


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