The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2003
Filed:
Apr. 19, 2001
Applicant:
Inventors:
Nobuhiro Tsuda, Tokyo, JP;
Koji Nii, Tokyo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 1/100 ;
U.S. Cl.
CPC ...
G11C 1/100 ;
Abstract
An SRAM memory cell is constituted by complementarily connecting first inverter composed of NMOS transistor and a PMOS transistor, and a second inverter composed of another NMOS transistor and another PMOS transistor. Still another NMOS transistor is so provided that its gate is connected to a node between the NMOS and PMOS transistors in the first inverter. Still another NMOS transistor is so provided that its gate is connected to a node between the NMOS and PMOS transistors in the second inverter. As a result, capacity values for gate capacities are added to the storage nodes.
Published as:
US2002012265A1; JP2002050183A; DE10132777A1; KR20020022125A; US6535417B2; KR100418233B1; TWI222638B;